Welcome everyone to this internal technical training session. In today’s technological landscape, storage chips serve as the “paper” and “workbench” of the digital world, and the evolution of their technology roadmap directly determines the performance ceiling of entire systems. To help you develop a comprehensive understanding of storage technologies, this course will thoroughly dissect the various segments of the storage‑chip market, providing a systematic overview—from underlying classifications and technical principles to key parameters and real‑world application scenarios—thus offering robust technical support for product development, market expansion, and customer service.

Chapter 1: The First Divide in Storage Chips: Volatile vs. Non-Volatile

The most fundamental criterion for classifying memory chips is whether data remains intact after power is removed. This physical characteristic determines the chip’s technological roadmap, its application scenarios, and its cost structure.

1. Volatile memory 
   • Characteristics : Data is lost immediately upon power loss. Its key advantages are extremely high speed and relatively low cost.
   • Positioning : As the system’s “working memory,” it is responsible for temporarily storing the data currently being processed by the CPU.
   • Representative products : DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory).
2. Non-Volatile Memory (Non-Volatile) 
   • Characteristics : Data is retained for the long term after power loss. Although read/write speeds are relatively slow, this ensures data persistence.
   • Positioning : As the system’s “long-term storage,” it is used to store the operating system, user files, and firmware code.
   • Representative products : NAND Flash, NOR Flash, and cutting-edge emerging memory technologies (such as PCRAM and MRAM).

Chapter 2: Volatile Memory: The Ultimate Trade-off Between Speed and Cost

In the realm of volatile memory, chips at different hierarchical levels assume distinct data‑scheduling roles, forming a seamless hierarchy that spans from CPU caches and system main memory to AI accelerators.

1. SRAM (Static Random-Access Memory): The CPU’s on-chip cache. 
   SRAM consists of a latch built from six transistors; as long as power is supplied, the data remains intact without requiring refresh. It offers extremely fast access speeds—on the order of 1 to 10 nanoseconds—but its drawbacks include a large chip footprint and high cost. Consequently, SRAM is typically integrated within the CPU as L1, L2, or L3 cache to alleviate the speed bottleneck of main memory.
2. DRAM (Dynamic Random Access Memory): the system’s main working platform 
   DRAM uses a “1 transistor + 1 capacitor” as its basic cell. Because the charge stored in the capacitor leaks over time, it must be refreshed every few tens of milliseconds to preserve data. DRAM is organized in an array and accessed via row and column addresses; its key performance metric is the CAS latency (CL). Today, mainstream DDR5 memory operates at frequencies up to 6,400 MT/s, delivering bandwidths of up to 51.2 GB/s, making it the dominant choice for both desktop and mobile systems.
3. HBM (High Bandwidth Memory): The Computing Power Engine of the AI Era 
   HBM is a high‑end variant of DRAM, specifically designed to address the “memory wall” challenge in training large AI models. It employs through‑silicon via (TSV) technology to vertically stack multiple layers of DRAM chips and features ultra‑wide interfaces—such as 1024 bits—that connect directly to GPUs. This 3D architecture enables HBM3 to achieve bandwidth exceeding 819 GB/s, while HBM3E surpasses 1 TB/s. In AI servers, HBM directly determines the upper limit of data throughput for compute‑intensive chips.

Chapter 3: NAND Flash—The Cornerstone of Mass Data Storage

As the mainstream technology for non-volatile storage, NAND flash is widely used in SSDs, mobile phone storage, and USB flash drives. Its core technology relies on the “floating-gate” structure, which modulates the transistor’s threshold voltage by trapping electrons, thereby enabling the storage of binary values 0 and 1.

1. The Evolution of Storage Density: From SLC to QLC 
   By packing more bits into a single memory cell, NAND flash has achieved a significant leap in capacity. SLC (1 bit) offers a write‑erase endurance of 100,000 cycles and is primarily used in industrial and military applications; MLC (2 bits) and TLC (3 bits) currently dominate both enterprise‑grade and consumer‑grade SSDs; while QLC (4 bits), with an endurance of around 300 erase/write cycles and very low cost, targets high‑capacity cold‑data storage.
2. 3D NAND: A Spatial Revolution from Planar to Three-Dimensional Architecture 
   To transcend the physical limits of 2D planar architectures, the industry has fully transitioned to 3D NAND. By vertically stacking memory cells like building floors, storage density per unit area has increased dramatically. Today, leading manufacturers have already achieved stacking technologies exceeding 300 layers, with future roadmaps aiming for 500 layers and even 1,000 layers—posing ongoing challenges in packaging, particularly in thermal management and signal integrity.

Chapter 4: Frontier Exploration: The Path to Breaking the Impasse in Next-Generation Memory Technologies

The industry has long been seeking a universal memory that combines “SRAM‑level speed, NAND‑level density, and nonvolatile data retention.” The following technologies represent the future direction of development:

• PCRAM (Phase-Change Memory) : It stores data by switching between crystalline and amorphous states, offering speeds a hundred times faster than NAND; however, its high cost has hindered its commercialization.
• MRAM (Magnetic Random Access Memory) It stores data by leveraging the magnetization orientation of magnetic tunnel junctions, offering an unlimited erase/write endurance and performance approaching that of SRAM. Currently, it is primarily used in automotive-grade and industrial control applications as a replacement for NOR Flash.
• ReRAM and FeRAM They focus on resistive‑change and ferroelectric polarization, emphasizing ultra‑low power consumption and exceptionally high endurance; currently, they are mainly used in niche markets such as IoT devices and smart cards.

Chapter 5: Analysis of Core Parameters and Terminal Application Scenarios

1. How do you evaluate the performance of memory chips? 
   • Bandwidth : Measuring data transfer rates, HBM’s bandwidth is tens of times that of DDR5.
   • Latency : The time from request to data return is on the order of nanoseconds for DRAM and microseconds for NAND.
   • IOPS and Durability Enterprise-grade SSDs require attention to DWPD (Drive Writes Per Day) and TBW (Total Bytes Written), as these metrics directly determine the product’s lifespan.
2. Technology Selection for Typical Use Cases 
   • Smartphone It adopts a combination of LPDDR (low-power RAM) and UFS (high-speed flash storage), balancing battery life with read/write performance.
   • AI server : It comes standard with HBM to meet ultra‑high bandwidth requirements, while also adopting the CXL interconnect protocol to expand the memory pool, thereby addressing capacity bottlenecks caused by excessively large model parameters.
   • Automotive electronics Automotive-grade storage must withstand extreme temperatures ranging from −40°C to 125°C, offer a 15-year service life, and maintain a zero-defect rate; it must also be certified to both AEC-Q100 and ISO 26262 functional safety standards.

Training Conclusion

Though small in size, storage chips are the cornerstone that underpins the entire digital world. From DRAM to NAND, and from HBM to CXL, each technological leap is redefining the boundaries of computing power. We hope that, through this training, all colleagues will gain a deep understanding of the diverse requirements different application scenarios place on storage technologies. In our future work, by choosing the right technology roadmap, we can double our system performance; and by precisely aligning with customer needs, LeaKin Technology will continue to lead in an increasingly competitive market.